Insertion phase variation compensation module and method of counteracting the effect of a phase offset introduced into a received signal

ABSTRACT

A communication system including an amplifier, a receiver, an analog to digital converter (ADC) and an insertion phase variation compensation module. The amplifier receives a communication signal. If the amplifier is enabled, the amplifier amplifies the communication signal and outputs the amplified communication signal to the receiver. If the amplifier is disabled, the amplifier passes the communication signal to the receiver without amplifying it. The receiver outputs an analog complex signal to the ADC. The ADC outputs a digital complex signal to the insertion phase variation compensation module which counteracts the effects of a phase offset intermittently introduced into the communication signal when the amplifier is enabled or disabled.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.10/736,381, filed Dec. 15, 2003, which claims the benefit of U.S.Provisional Application No. 60/476,753, filed Jun. 6, 2003, which isincorporated by reference as if fully set forth.

FIELD OF THE INVENTION

The present invention generally relates to wireless communicationsystems. More particularly, the present invention relates to digitalsignal processing (DSP) techniques used to compensate for phasevariations associated with switching an amplifier on or off.

BACKGROUND

In a conventional phase-sensitive communication system, a receiver usesan amplifier to control the power level of a radio frequency (RF) and/orintermediate frequency (IF) communication signals. Typically, one ormore amplifiers, (i.e., gain stages), are used to amplify thecommunication signals. Preferably, low noise amplifiers (LNAs) are usedbecause they have a low noise figure, and thus they do not significantlyraise the noise floor of the communication system.

Because the communication signals have different power levels when theyare received, the amplifier(s) is intermittently switched on or offwhich causes sizable phase offsets to be introduced into thecommunication signals. Such phase offsets degrade the performance of thephase-sensitive communication system. A method and system for cancelingthe phase offset of communication signals caused by turning an amplifieron or off is desired.

SUMMARY

The present invention is incorporated into a communication system whichincludes an amplifier, (i.e., gain stage), a receiver, an analog todigital converter (ADC) and an insertion phase variation compensationmodule. The amplifier receives a communication signal. If the amplifieris enabled, the amplifier amplifies the communication signal and outputsthe amplified communication signal to the receiver. If the amplifier isdisabled, the amplifier passes the communication signal to the receiverwithout amplifying it. The receiver outputs an analog complex signal tothe ADC. The ADC outputs a digital complex signal to the insertion phasevariation compensation module which counteracts the effects of a phaseoffset intermittently introduced into the communication signal when theamplifier is enabled or disabled (i.e., turned on or off). The analogand digital complex signals include in-phase (I) and quadrature signalcomponents.

An amplification control signal is provided to the amplifier on anintermittent basis. The amplification control signal either turns on orturns off the amplifier. An estimate of the phase offset is provided tothe insertion phase variation compensation module as a function of theamplification control signal.

The insertion phase variation compensation module may receive thedigital I and Q signal components from the ADC and output altered I andQ signal components having different phase characteristics than thedigital I and Q components. The communication system may further includea modem which receives the altered I and Q signal components. The modemmay include a processor which generates the amplification controlsignal. The processor may calculate how much power is input to the ADC.

The communication system may further include a look up table (LUT) incommunication with the processor and the insertion phase variationcompensation module. The LUT may receive the amplification controlsignal from the processor and provide an estimate of the phase offset tothe insertion phase variation compensation module as a function of theamplification control signal. The provided estimate may include a Sinfunction and a Cos function of a phase offset, x. The insertion phasevariation compensation module may have a real, Re, input associated witha digital I signal component and an imaginary, Im, input associated witha Q signal component and, based on the estimate provided by the LUT, theinsertion phase variation compensation module may output an I signalcomponent having a phase that is adjusted in accordance with thefunction (Cos(x)×Re)−(Sin(x)×Im) and a Q signal component having a phasethat is adjusted in accordance with the function(Sin(x)×Re)+(Cos(x)×Im).

The communication signal may include first and second time slotsseparated by a guard period. During the guard period, which occurs afterdata in the first time slot is received by the amplifier and isprocessed, the amplification control signal may be provided to theamplifier and, in response, the amplifier may be either enabled ordisabled. When data in the first time slot is received by the amplifierwhen it is disabled, the data in the second time slot may received bythe amplifier when it is enabled. When data in the first time slot isreceived by the amplifier when it is enabled, the data in the secondtime slot is received by the amplifier when it is disabled. Also, duringthe guard period, the estimate of the phase offset may be provided tothe insertion phase variation compensation module and the insertionphase variation compensation module may adjust the phase of thecommunication signal based on the provided estimate.

BRIEF DESCRIPTION OF THE DRAWINGS

A more detailed understanding of the invention may be had from thefollowing description of a preferred example, given by way of exampleand to be understood in conjunction with the accompanying drawingwherein:

FIG. 1 is a block diagram of a communication system including aninsertion phase variation compensation module that cancels out a phaseoffset intermittently introduced into a communication signal by turningon or off an amplifier in accordance with the present invention;

FIG. 2 illustrates an exemplary communication signal having a guardperiod which occurs between two time slots;

FIG. 3 is an exemplary configuration of the insertion phase variationcompensation module of FIG. 1;

FIG. 4 is a flow chart of a process including steps implemented tocounteract the effects of a phase offset intermittently introduced intoa communication signal by disabling the amplifier of FIG. 1;

FIG. 5 is a flow chart of a process including steps implemented tocounteract the effects of a phase offset intermittently introduced intoa communication signal by enabling the amplifier of FIG. 1;

FIG. 6 is a flow chart of a process including steps implemented tocounteract the effects of a phase offset intermittently introduced intoa communication signal by disabling the amplifier of FIG. 1 during aguard period; and

FIG. 7 is a flow chart of a process including steps implemented tocounteract the effects of a phase offset intermittently introduced intoa communication signal by enabling the amplifier of FIG. 1 during aguard period.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention provides a method and system that cancels out thephase difference introduced into an RF or IF communication signal,(i.e., data stream), by turning on or off an amplifier.

Preferably, the method and system disclosed herein is incorporated intoa wireless transmit/receive unit (WTRU). Hereafter, a WTRU includes butis not limited to a user equipment, mobile station, fixed or mobilesubscriber unit, pager, or any other type of device capable of operatingin a wireless environment. The features of the present invention may beincorporated into an integrated circuit (IC) or be configured in acircuit comprising a multitude of interconnecting components.

The present invention is applicable to communication systems using timedivision duplex (TDD), time division multiple access (TDMA), frequencydivision duplex (FDD), code division multiple access (CDMA), CDMA 2000,time division synchronous CDMA (TDSCDMA), orthogonal frequency divisionmultiplexing (OFDM) or the like.

FIG. 1 is a block diagram of a communication system 100 operating inaccordance with the present invention. Communication system 100 includesan amplifier (e.g., LNA) 105, a receiver 110, an analog to digitalconverter (ADC) 115, an insertion phase variation compensation module120 and a modem 125. The amplifier 105 and the ADC 115 may beincorporated into receiver 110. Furthermore, the insertion phasevariation compensation module 120 may be incorporated into the modem125. The modem 125 includes a processor 130 which calculates how muchpower is input to the ADC 115. The modem 125 receives complex I and Qsignal components 135, 140, from the insertion phase variationcompensation module 120, and, via processor 130, outputs anamplification control signal 145 to the amplifier 105. The amplificationcontrol signal 145 either enables or disables the amplifier 105. Theamplifier 105 may consist of a single gain stage or multiple gain stages(i.e., the amplifier 105 may represent a chain of amplifiers which areall controlled by the same amplification control signal 145). When theamplifier 105 is disabled, (i.e., turned off), an RF and/or IFcommunication signal 150 passes through amplifier 105 without beingamplified. When the amplifier 105 is enabled, (i.e., turned on), thecommunication signal 150 is amplified accordingly. The amplificationcontrol signal 145 is also output from the processor 130 to a look uptable (LUT) 155, which uses the amplification control signal 145 toprovide the insertion phase variation compensation module 120 with anestimate of the phase offset that is introduced into the communicationsignal 150.

Each time the amplifier 105 is enabled or disabled, an associated phaseoffset, i.e., phase rotation, may be introduced into the communicationsignal 150. The phase offset is considerable. For example, the phase ofthe communication signal 150 may change by a significant amount (i.e.,rotate, by 80 or 90 degrees). An estimate of the phase offset (x) as afunction of the state (i.e., turned on or turned off) of amplifier 105may be determined by accessing the LUT 155, a predefined polynomial, orany other method that can map the status of the amplifier, i.e., enabledor disabled, to a phase offset estimate.

FIG. 2 illustrates an example of a communication signal 150 having aguard period 205 which occurs between two time slots 210, 215. Thisexemplary communication signal may be used under the presumption thatcommunication system 100 is a TDD, TDMA, TDSCDMA or other time-slottedcommunication system. In this example, data in the communication signal150 is communicated via the time slots 210 and 215. Thus, the only timethat the amplifier 105 may be enabled or disabled without disrupting thedata in the time slots 210, 215, of communication signal 150, is duringthe guard period 205. Any phase offset resulting from turning on or offthe amplifier 105 is cancelled by the insertion phase variationcompensation module during the same guard period 205 such that the phaseoffset or the cancellation thereof will not degrade the quality of thedata received in the time slot 215 that occurs after the guard period205 expires.

FIG. 3 shows an exemplary configuration of the insertion phase variationcompensation module 120 which rotates the phase characteristics of the Iand Q signal components of a digital complex signal output from the ADC115 based on the amplification control signal 145, so as to counteractthe effects of a phase offset intermittently introduced into acommunication signal 150 by the amplifier 105. Thus, the modem 125 isnot affected by the phase offset and the performance of thecommunication system 100 is not degraded.

As shown in FIG. 3, the insertion phase variation compensation module120 includes multipliers 305, 310, 315, 320 and adders 325 and 330. Theinsertion phase variation compensation module 120 receives a real (Re) Isignal component 350 and an imaginary (jIm) Q signal component 360 fromthe ADC 115 and rotates the phase of the signal components Re and jIm byx degrees (e^(jx)) as described by Equation 1 below:(Re+jIm)×e ^(jx)=(Re+jIm)×(Cos(x)+j Sin(x))  Equation 1

The outcome of the real output, {circumflex over (R)} e, is described byEquation 2 below:{circumflex over (R)}e=(Cos(x)×Re)×(j²×Sin(x)×Im)=(Cos(x)×Re)−(Sin(x)×Im)  Equation 2Note that if x is close to zero, then Cos(x)=1.0 and Sin(x)=x, asdescribed by Equation 3 below:{circumflex over (R)}e=Re−Im×x  Equation 3

The output of the imaginary output, Im, is described by Equation 4below:Îm=(Sin( x)×Re)+(Cos(x)×Im)  Equation 4Note that if x is close to zero, then Cos(x)=1.0 and Sin(x)=x, asdescribed by Equation 5 below:Îm=Im+Re×x  Equation 5

Thus, as depicted by Equation 2, the real signal component 350 ismultiplied by a Cos(x) function 380 specified by the LUT 155 via themultiplier 315 and the imaginary signal component 360 is multiplied by aSin (x) function 370 also specified by the LUT 155 via the multiplier310, whereby the output of the multiplier 310 is subtracted from theoutput of the multiplier 315 by the adder 325. Furthermore, as depictedby Equation 4, the real signal component 350 is multiplied by a Sin(x)function 370 specified by the LUT 155 via the multiplier 305 and theimaginary signal component 360 is multiplied by a Cos(x) function 380also specified by the LUT 155 via the multiplier 320, whereby the outputof the multiplier 320 is added to the output of the multiplier 305 bythe adder 330.

In one embodiment, only a single phase compensation value is required tocompensate for phase offsets caused by switching amplifier 105 on oroff, whereby the insertion phase variation compensation module 120 maybe disabled, using physical switching hardware, when the amplifier 105is turned on. When the insertion phase variation compensation module 120is disabled, the respective input and output I and Q signal componentsof the insertion phase variation module 120 are the same and the I and Qsignal components pass through the insertion phase variationcompensation module 120 unaffected. When the amplifier 105 is turnedoff, the insertion phase variation compensation module 120 is enabled,causing it to compensate for a phase offset by a phase adjustment X,caused by turning the amplifier 105 off. When the amplifier 105 isturned back on, the insertion phase variation compensation module 120 isagain disabled, causing the phase to change from X to zero, whichcompensates for the phase offset caused by turning the amplifier 105back on.

Alternatively, instead of using additional switching hardware, a firstregister (i.e., memory location) for storing the Sin(x) and a secondregister for storing the Cos(x) may be used to control the insertionphase variation compensation module 120 in similar fashion as describedabove (i.e., a zero phase offset or a phase offset x).

In another embodiment, a plurality of registers may be used to set theinsertion phase variation compensation module 120 to any desired phasecompensation value. The plurality of registers may include a firstregister for storing Sin(x), a second register for storing Sin(0), athird register for storing Cos(x) and a fourth register for storingCos(0), where Sin(0)=0 and Cos(0)=1. If the amplifier 105 is turned on,the data in the second and fourth registers is applied as phase rotationerror to the insertion phase variation compensation module 120. If theamplifier 105 is turned off, the data in the first and third registersis applied as phase rotation error to the insertion phase variationcompensation module 120.

FIG. 4 is a flow chart of a process 400 including steps implemented tocounteract the effects of a phase offset intermittently introduced intothe communication signal 150 by disabling the amplifier 105. The process400 may be implemented in any type of communication system. In step 405,the amplification control signal 145 is provided to an enabled amplifier105 configured to receive a communication signal 150. In step 410, theenabled amplifier 105 is disabled in response to the amplificationcontrol signal 145, thus causing a phase offset to be intermittentlyintroduced into the communication signal 150. In step 415, an estimateof the phase offset is provided to the insertion phase variationcompensation module 120 as a function of the amplification controlsignal 145. In step 420, the insertion phase variation compensationmodule 120 adjusts the phase of the communication signal 150 based onthe provided estimate.

FIG. 5 is a flow chart of a process 500 including steps implemented tocounteract the effects of a phase offset intermittently introduced intothe communication signal 150 by enabling the amplifier 105. The process500 may be implemented in any type of communication system. In step 505,the amplification control signal 145 is provided to a disabled amplifier105 configured to receive a communication signal 150. In step 510, thedisabled amplifier 105 is enabled in response to the amplificationcontrol signal 145, thus causing a phase offset to be intermittentlyintroduced into the communication signal 150. In step 515, an estimateof the phase offset is provided to the insertion phase variationcompensation module 120 as a function of the amplification controlsignal 145. In step 520, the insertion phase variation compensationmodule 120 adjusts the phase of the communication signal 150 based onthe provided estimate.

FIG. 6 is a flow chart of a process 600 including steps implemented tocounteract the effects of a phase offset intermittently introduced intothe communication signal 150 by disabling the amplifier 105 during aguard period. The process 600 may be implemented in a TDD, TDMA, TDSCDMAor other time-slotted communication system. In step 605, data in a firsttime slot 210 of a communication signal 150 is received by an enabledamplifier 105 and is processed. In step 610, the amplification controlsignal 145 is provided to the enabled amplifier 105 during a guardperiod 205 occurring after the first time slot 210 expires. In step 615,the enabled amplifier 105 is disabled during the guard period 205 inresponse to the amplification control signal 145, thus causing a phaseoffset to be intermittently introduced into the communication signal150. In step 620, an estimate of the phase offset is provided during theguard period 205 to the insertion phase variation compensation module120 as a function of the amplification control signal 145. In step 625,the insertion phase variation compensation module 120 adjusts, duringthe guard period 205, the phase of the communication signal 150 based onthe provided estimate. In step 630, data in a second time slot 215 ofthe communication signal 150 is received by the disabled amplifier 105after the guard period 205 and is processed.

FIG. 7 is a flow chart of a process 700 including steps implemented tocounteract the effects of a phase offset intermittently introduced intothe communication signal 150 by enabling the amplifier 105 during aguard period. The process 700 may be in a TDD, TDMA, TDSCDMA or othertime-slotted communication system. In step 705, data in a first timeslot 210 of a communication signal 150 is received by a disabledamplifier 105 and is processed. In step 710, the amplification controlsignal 145 is provided to the disabled amplifier 105 during a guardperiod 205 occurring after the first time slot 210 expires. In step 715,the disabled amplifier 105 is enabled during the guard period 205 inresponse to the amplification control signal 145, thus causing a phaseoffset to be intermittently introduced into the communication signal150. In step 720, an estimate of the phase offset is provided during theguard period 205 to the insertion phase variation compensation module120 as a function of the amplification control signal 145. In step 725,the insertion phase variation compensation module 120 adjusts, duringthe guard period 205, the phase of the communication signal 150 based onthe provided estimate. In step 730, data in a second time slot 215 ofthe communication signal 150 is received by the enabled amplifier 105after the guard period 205 and is processed.

While this invention has been particularly shown and described withreference to preferred embodiments, it will be understood by thoseskilled in the art that various changes in form and details may be madetherein without departing from the scope of the invention describedhereinabove.

1. A method for counteracting the effect of a phase offset, x,introduced into a received signal, the method comprising: (a) receivinga real input, Re, associated with a digital in-phase (I) signalcomponent; (b) receiving an imaginary input, Im, associated with aquadrature (Q) signal component; and (c) generating an I signalcomponent having a phase that is adjusted in accordance with thefollowing function: (Cos(x)×Re)−(Sin(x)×Im).
 2. A method forcounteracting the effect of a phase offset, x, introduced into areceived signal, the method comprising: (a) receiving a real input, Re,associated with a digital in-phase (I) signal component; (b) receivingan imaginary input, Im, associated with a quadrature (Q) signalcomponent; and (c) generating a Q signal component having a phase thatis adjusted in accordance with the following function:((Sin(x)×Re)+(Cos(x)×Im).
 3. An insertion phase variation compensationmodule for counteracting the effect of a phase offset, x, introducedinto a received signal, the insertion phase variation compensationmodule comprising: (a) a real input, Re, associated with a digitalin-phase (I) signal component; (b) an imaginary input, Im, associatedwith a quadrature (Q) signal component; (c) an imaginary outputconfigured to output an I signal component having a phase that isadjusted in accordance with the following function:(Cos(x)×Re)−(Sin(x)×Im).
 4. The insertion phase variation compensationmodule of claim 3 further comprising: (d) a first multiplier formultiplying Cos(x) by Re to generate a first product; (e) a secondmultiplier for multiplying Sin(x) by Im to generate a second product;and (f) an adder for subtracting the second product from the firstproduct to generate the phase-adjusted I signal component.
 5. Anintegrated circuit (IC) comprising the insertion phase variationcompensation module of claim
 3. 6. A wireless transmit/receive unit(WTRU) comprising the insertion phase variation compensation module ofclaim
 3. 7. An insertion phase variation compensation module forcounteracting the effect of a phase offset, x, introduced into areceived signal, the insertion phase variation compensation modulecomprising: (a) a real input, Re, associated with a digital in-phase (I)signal component; (b) an imaginary input, Im, associated with aquadrature (Q) signal component; and (c) a quadrature output configuredto output a Q signal component having a phase that is adjusted inaccordance with the following function: (Sin(x)×Re)+(Cos(x)×Im).
 8. Theinsertion phase variation compensation module of claim 7 furthercomprising: (d) a first multiplier for multiplying Sin(x) by Re togenerate a first product; (e) a second multiplier for multiplying Cos(x)by Im to generate a second product; and (f) an adder for adding thefirst and second products to generate the phase-adjusted Q signalcomponent.
 9. An integrated circuit (IC) comprising the insertion phasevariation compensation module of claim
 7. 10. A wirelesstransmit/receive unit (WTRU) comprising the insertion phase variationcompensation module of claim 7.